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gen/fhdl/memory: Fix dual clock memory pattern (previous pattern is no longer supported by Yosys), thanks @gregdavill. 

See https://github.com/enjoy-digital/litex/issues/1003.
This commit is contained in:
Florent Kermarrec 2021-10-13 11:33:43 +02:00
parent 8fbd1b84a4
commit fd354c5759
1 changed files with 7 additions and 0 deletions
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7
litex/gen/fhdl/memory.py
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@ -21,6 +21,13 @@ def memory_emit_verilog(memory, ns, add_data_file):
adr_regs = {}
data_regs = {}
# https://github.com/enjoy-digital/litex/issues/1003
# FIXME: Verify behaviour with the different FPGA toolchains.
clocks = [port.clock for port in memory.ports]
if clocks.count(clocks[0]) != len(clocks):
for port in memory.ports:
port.mode = READ_FIRST
for port in memory.ports:
if not port.async_read:
if port.mode == WRITE_FIRST: