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cores/hyperbus: Switch default latency_mode to variable.

This commit is contained in:
Florent Kermarrec 2024-04-16 10:19:59 +02:00
parent 62b9c64212
commit fd6f913525
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/hyperbus.py
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@ -33,7 +33,7 @@ class HyperRAM(LiteXModule):
Parameters: Parameters:
pads (Record) : Interface to the HyperRAM connection pads. pads (Record) : Interface to the HyperRAM connection pads.
latency (int, optional) : Initial latency setting, defaults to 6. latency (int, optional) : Initial latency setting, defaults to 6.
latency_mode (str, optional) : Specifies the latency mode ('fixed' or 'variable'), defaults to 'fixed'. latency_mode (str, optional) : Specifies the latency mode ('fixed' or 'variable'), defaults to 'variable'.
sys_clk_freq (float, optional) : System clock frequency in Hz. sys_clk_freq (float, optional) : System clock frequency in Hz.
with_csr (bool, optional) : Enables CSR interface for Latency/Registers configuration, defaults to True. with_csr (bool, optional) : Enables CSR interface for Latency/Registers configuration, defaults to True.
@ -41,7 +41,7 @@ class HyperRAM(LiteXModule):
pads (Record) : Platform pads of HyperRAM. pads (Record) : Platform pads of HyperRAM.
bus (wishbone.Interface) : Wishbone Interface. bus (wishbone.Interface) : Wishbone Interface.
""" """
def __init__(self, pads, latency=6, latency_mode="fixed", sys_clk_freq=None, with_csr=True): def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=None, with_csr=True):
self.pads = pads self.pads = pads
self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word") self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")