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gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog.

This commit is contained in:
Florent Kermarrec 2023-11-03 11:29:48 +01:00
parent e6d950bcb0
commit fe19ee464e
2 changed files with 10 additions and 9 deletions
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15
litex/gen/fhdl/memory.py
View File

@ -2,18 +2,19 @@
# This file is part of LiteX (Adapted from Migen for LiteX usage).
#
# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2021-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from migen.fhdl.structure import *
from migen.fhdl.module import *
from migen.fhdl.structure import *
from migen.fhdl.module import *
from migen.fhdl.bitcontainer import bits_for
from migen.fhdl.tools import *
from migen.fhdl.verilog import _printexpr as verilog_printexpr
from migen.fhdl.specials import *
from migen.fhdl.tools import *
from migen.fhdl.verilog import _printexpr as verilog_printexpr
from migen.fhdl.specials import *
# LiteX Memory Verilog Generation ------------------------------------------------------------------
def memory_emit_verilog(name, memory, namespace, add_data_file):
def _memory_generate_verilog(name, memory, namespace, add_data_file):
# Helpers.
# --------

4
litex/gen/fhdl/verilog.py
View File

@ -527,8 +527,8 @@ def _generate_specials(name, overrides, specials, namespace, add_data_file, attr
r += _generate_attribute(special.attr, attr_translate)
# Replace Migen Memory's emit_verilog with LiteX's implementation.
if isinstance(special, Memory):
from litex.gen.fhdl.memory import memory_emit_verilog
pr = memory_emit_verilog(name, special, namespace, add_data_file)
from litex.gen.fhdl.memory import _memory_generate_verilog
pr = _memory_generate_verilog(name, special, namespace, add_data_file)
else:
pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
if pr is None: