fhdl/verilog: Remove create_clock_domains (not used in LiteX).

litex/build/generic_platform.py

@@ -432,10 +432,7 @@ class GenericPlatform:
         return named_sc, named_pc
 
     def get_verilog(self, fragment, **kwargs):
-        return verilog.convert(
+        return verilog.convert(fragment, self.constraint_manager.get_io_signals(), **kwargs)
-            fragment,
-            self.constraint_manager.get_io_signals(),
-            create_clock_domains=False, **kwargs)
 
     def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
         return edif.convert(

litex/gen/fhdl/verilog.py

@@ -470,7 +470,6 @@ class DummyAttrTranslate(dict):
 def convert(f, ios=set(), name="top",
     special_overrides    = dict(),
     attr_translate       = DummyAttrTranslate(),
-    create_clock_domains = True,
     blocking_assign      = False,
     regular_comb         = True):
 
@@ -486,18 +485,12 @@ def convert(f, ios=set(), name="top",
         # Try to get Clock Domain.
         try:
             f.clock_domains[cd_name]
-        # If not found, create it if enabled:
+        # If not found, raise Error.
         except:
-            if create_clock_domains:
+            msg = f"""Unresolved clock domain {cd_name}, availables:\n"""
-                cd = ClockDomain(cd_name)
+            for f in f.clock_domains:
-                f.clock_domains.append(cd)
+                msg += f"- {f.name}\n"
-                ios |= {cd.clk, cd.rst}
+            raise Exception(msg)
-            # Or raise Error.
-            else:
-                msg = f"""Unresolved clock domain {cd_name}, availables:\n"""
-                for f in f.clock_domains:
-                    msg += f"- {f.name}\n"
-                raise Exception(msg)
 
     # Lower complex slices.
     f = lower_complex_slices(f)