remove Layer in module names
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b9a9e075fd
commit
fe875ea650
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@ -13,7 +13,7 @@ from_rx = [
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("det", 32)
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("det", 32)
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]
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]
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class SATALinkLayerTX(Module):
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class SATALinkTX(Module):
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def __init__(self, phy):
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def __init__(self, phy):
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self.sink = Sink(link_layout(32))
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self.sink = Sink(link_layout(32))
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self.from_rx = Sink(from_rx)
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self.from_rx = Sink(from_rx)
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@ -111,7 +111,7 @@ class SATALinkLayerTX(Module):
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)
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)
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)
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)
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class SATALinkLayerRX(Module):
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class SATALinkRX(Module):
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def __init__(self, phy):
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def __init__(self, phy):
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self.source = Source(link_layout(32))
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self.source = Source(link_layout(32))
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self.to_tx = Source(from_rx)
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self.to_tx = Source(from_rx)
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@ -212,9 +212,9 @@ class SATALinkLayerRX(Module):
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self.to_tx.det.eq(det)
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self.to_tx.det.eq(det)
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]
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]
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class SATALinkLayer(Module):
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class SATALink(Module):
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def __init__(self, phy):
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def __init__(self, phy):
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self.submodules.tx = SATALinkLayerTX(phy)
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self.submodules.tx = SATALinkTX(phy)
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self.submodules.rx = SATALinkLayerRX(phy)
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self.submodules.rx = SATALinkRX(phy)
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self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
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self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
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self.sink, self.source = self.tx.sink, self.rx.source
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self.sink, self.source = self.tx.sink, self.rx.source
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@ -5,7 +5,7 @@ from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from migen.sim.generic import run_simulation
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from lib.sata.std import *
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from lib.sata.std import *
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from lib.sata.link import SATALinkLayer
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from lib.sata.link import SATALink
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from lib.sata.test.bfm import *
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from lib.sata.test.bfm import *
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from lib.sata.test.common import *
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from lib.sata.test.common import *
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@ -67,7 +67,7 @@ class TB(Module):
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def __init__(self):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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self.submodules.bfm = BFM(phy_debug=False,
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link_random_level=50, transport_debug=False, transport_loopback=True)
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link_random_level=50, transport_debug=False, transport_loopback=True)
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self.submodules.link_layer = SATALinkLayer(self.bfm.phy)
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self.submodules.link = SATALink(self.bfm.phy)
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self.submodules.streamer = LinkStreamer()
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self.submodules.streamer = LinkStreamer()
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streamer_ack_randomizer = AckRandomizer(link_layout(32), level=50)
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streamer_ack_randomizer = AckRandomizer(link_layout(32), level=50)
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@ -77,8 +77,8 @@ class TB(Module):
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self.submodules += logger_ack_randomizer
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self.submodules += logger_ack_randomizer
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self.comb += [
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self.comb += [
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Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
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Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
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Record.connect(streamer_ack_randomizer.source, self.link_layer.sink),
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Record.connect(streamer_ack_randomizer.source, self.link.sink),
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Record.connect(self.link_layer.source, logger_ack_randomizer.sink),
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Record.connect(self.link.source, logger_ack_randomizer.sink),
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Record.connect(logger_ack_randomizer.source, self.logger.sink)
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Record.connect(logger_ack_randomizer.source, self.logger.sink)
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]
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]
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@ -5,8 +5,8 @@ from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from migen.sim.generic import run_simulation
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from lib.sata.std import *
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from lib.sata.std import *
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from lib.sata.link import SATALinkLayer
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from lib.sata.link import SATALink
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from lib.sata.transport import SATATransportLayer
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from lib.sata.transport import SATATransport
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from lib.sata.test.bfm import *
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from lib.sata.test.bfm import *
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from lib.sata.test.common import *
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from lib.sata.test.common import *
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@ -15,8 +15,8 @@ class TB(Module):
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def __init__(self):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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self.submodules.bfm = BFM(phy_debug=False,
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link_random_level=0, transport_debug=True, transport_loopback=True)
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link_random_level=0, transport_debug=True, transport_loopback=True)
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self.submodules.link = SATALinkLayer(self.bfm.phy)
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self.submodules.link = SATALink(self.bfm.phy)
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self.submodules.transport = SATATransportLayer(self.link)
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self.submodules.transport = SATATransport(self.link)
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def gen_simulation(self, selfp):
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def gen_simulation(self, selfp):
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for i in range(100):
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for i in range(100):
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@ -18,7 +18,7 @@ def _encode_cmd(obj, layout, signal):
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r.append(signal[start:end].eq(item))
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r.append(signal[start:end].eq(item))
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return r
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return r
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class SATATransportLayerTX(Module):
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class SATATransportTX(Module):
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def __init__(self, link):
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def __init__(self, link):
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self.sink = sink = Sink(transport_tx_layout(32))
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self.sink = sink = Sink(transport_tx_layout(32))
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@ -136,7 +136,7 @@ def _decode_cmd(signal, layout, obj):
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r.append(item.eq(signal[start:end]))
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r.append(item.eq(signal[start:end]))
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return r
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return r
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class SATATransportLayerRX(Module):
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class SATATransportRX(Module):
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def __init__(self, link):
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def __init__(self, link):
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self.source = source = Source(transport_rx_layout(32))
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self.source = source = Source(transport_rx_layout(32))
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@ -274,8 +274,8 @@ class SATATransportLayerRX(Module):
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self.comb += cmd_done.eq(cnt==cmd_len)
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self.comb += cmd_done.eq(cnt==cmd_len)
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self.comb += link.source.ack.eq(cmd_receive | (data_receive & source.ack))
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self.comb += link.source.ack.eq(cmd_receive | (data_receive & source.ack))
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class SATATransportLayer(Module):
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class SATATransport(Module):
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def __init__(self, link):
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def __init__(self, link):
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self.submodules.tx = SATATransportLayerTX(link)
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self.submodules.tx = SATATransportTX(link)
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self.submodules.rx = SATATransportLayerRX(link)
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self.submodules.rx = SATATransportRX(link)
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self.sink, self.source = self.tx.sink, self.rx.source
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self.sink, self.source = self.tx.sink, self.rx.source
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