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https://github.com/enjoy-digital/litex.git
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build/efinix/ifacewriter: Go a bit further in DRAM integration.
This commit is contained in:
Florent Kermarrec
parent
a742731d26
commit
feca1c472d
1 changed files with 65 additions and 25 deletions
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@ -210,14 +210,27 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd += "# ---------- END PLL {} ---------\n\n".format(name)
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return cmd
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def generate_pll_dram(self):
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return """
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design.create_block("pll_dram", block_type="PLL")
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design.set_property("pll_dram", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
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design.gen_pll_ref_clock("pll_dram", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="clk50", ext_refclk_no="1")
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design.set_property("pll_dram","LOCKED_PIN","pll_dram_locked", block_type="PLL")
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design.set_property("pll_dram","RSTN_PIN","pll_dram_rstn", block_type="PLL")
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design.set_property("pll_dram", {"CLKOUT0_PIN" : "pll_dram_CLKOUT0"}, block_type="PLL")
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design.set_property("pll_dram","CLKOUT0_PHASE","0","PLL")
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calc_result = design.auto_calc_pll_clock("pll_dram", {"CLKOUT0_FREQ": "400.0"})
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"""
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def generate(self, partnumber):
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output = ""
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for b in self.blocks:
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if b["type"] == "PLL":
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output += self.generate_pll(b, partnumber)
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if b["type"] == "PLL_DRAM":
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output += self.generate_pll_dram()
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if b["type"] == "GPIO":
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output += self.generate_gpio(b)
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return output
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def footer(self):
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@ -285,32 +298,59 @@ design.save()"""
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)
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gen_pin_target0 = et.SubElement(ddr, "efxpt:gen_pin_target0")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wdata", type_name=f"WDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wready", type_name=f"WREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wid", type_name=f"WID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bready", type_name=f"BREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rdata", type_name=f"RDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aid", type_name=f"AID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bvalid", type_name=f"BVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rlast", type_name=f"RLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bid", type_name=f"BID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_asize", type_name=f"ASIZE_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_atype", type_name=f"ATYPE_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aburst", type_name=f"ABURST_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wvalid", type_name=f"WVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wlast", type_name=f"WLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aaddr", type_name=f"AADDR_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rid", type_name=f"RID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_avalid", type_name=f"AVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rvalid", type_name=f"RVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_alock", type_name=f"ALOCK_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rready", type_name=f"RREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rresp", type_name=f"RRESP_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wstrb", type_name=f"WSTRB_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aready", type_name=f"AREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_alen", type_name=f"ALEN_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wdata", type_name=f"WDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wready", type_name=f"WREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wid", type_name=f"WID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bready", type_name=f"BREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rdata", type_name=f"RDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aid", type_name=f"AID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bvalid", type_name=f"BVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rlast", type_name=f"RLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bid", type_name=f"BID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_asize", type_name=f"ASIZE_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_atype", type_name=f"ATYPE_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aburst", type_name=f"ABURST_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wvalid", type_name=f"WVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wlast", type_name=f"WLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aaddr", type_name=f"AADDR_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rid", type_name=f"RID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_avalid", type_name=f"AVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rvalid", type_name=f"RVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alock", type_name=f"ALOCK_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rready", type_name=f"RREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rresp", type_name=f"RRESP_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wstrb", type_name=f"WSTRB_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aready", type_name=f"AREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alen", type_name=f"ALEN_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi_clk", type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false")
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gen_pin_target1 = et.SubElement(ddr, "efxpt:gen_pin_target1")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wdata", type_name=f"WDATA_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wready", type_name=f"WREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wid", type_name=f"WID_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bready", type_name=f"BREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rdata", type_name=f"RDATA_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aid", type_name=f"AID_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bvalid", type_name=f"BVALID_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rlast", type_name=f"RLAST_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bid", type_name=f"BID_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_asize", type_name=f"ASIZE_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_atype", type_name=f"ATYPE_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aburst", type_name=f"ABURST_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wvalid", type_name=f"WVALID_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wlast", type_name=f"WLAST_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aaddr", type_name=f"AADDR_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rid", type_name=f"RID_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_avalid", type_name=f"AVALID_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rvalid", type_name=f"RVALID_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alock", type_name=f"ALOCK_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rready", type_name=f"RREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rresp", type_name=f"RRESP_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wstrb", type_name=f"WSTRB_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aready", type_name=f"AREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alen", type_name=f"ALEN_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi_clk", type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false")
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gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
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et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_RST", is_bus="false")
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et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SCL_IN", is_bus="false")
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