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fhdl/specials/memory: do not write address register for async reads

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This commit is contained in:
Sebastien Bourdeauducq 2013-04-25 13:30:05 +02:00
parent 6c08cd67aa
commit fee228a09f
1 changed files with 5 additions and 5 deletions
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10
migen/fhdl/specials.py
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@ -258,11 +258,11 @@ class Memory(Special):
elif port.mode == NO_CHANGE: elif port.mode == NO_CHANGE:
rd = "\tif (!" + gn(port.we) + ")\n" \ rd = "\tif (!" + gn(port.we) + ")\n" \
+ "\t\t" + bassign + "\t\t" + bassign
if port.re is None: if port.re is None:
r += rd r += rd
else: else:
r += "\tif (" + gn(port.re) + ")\n" r += "\tif (" + gn(port.re) + ")\n"
r += "\t" + rd.replace("\n\t", "\n\t\t") r += "\t" + rd.replace("\n\t", "\n\t\t")
r += "end\n\n" r += "end\n\n"
for port in memory.ports: for port in memory.ports: