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cores/video/VideoVGAPHY: Add optional clk support. 

Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync)
but require the clock.
This commit is contained in:
Florent Kermarrec 2021-04-29 10:40:24 +02:00
parent 87ebdea5a7
commit fefc5aae66
1 changed files with 4 additions and 0 deletions
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4
litex/soc/cores/video.py
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@ -667,6 +667,10 @@ class VideoVGAPHY(Module):
# Always ack Sink, no backpressure. # Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1) self.comb += sink.ready.eq(1)
# Drive VGA Clk (Optional).
if hasattr(pads, "clk"):
self.comb += pads.clk.eq(ClockSignal(clock_domain))
# Drive VGA Conrols. # Drive VGA Conrols.
self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))