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fhdl/verilog: avoid reg initialization in printheader when reset is not an int. 

We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
This commit is contained in:
Florent Kermarrec 2015-04-10 17:18:07 +02:00
parent 181aeb4791
commit ff23960657
1 changed files with 5 additions and 1 deletions
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6
migen/fhdl/verilog.py
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@ -172,7 +172,11 @@ def _printheader(f, ios, name, ns):
if sig in wires: if sig in wires:
r += "wire " + _printsig(ns, sig) + ";\n" r += "wire " + _printsig(ns, sig) + ";\n"
else: else:
r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n" if isinstance(sig.reset, int):
resetexpr = " = " + _printexpr(ns, sig.reset)[0]
else:
resetexpr = ""
r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
r += "\n" r += "\n"
return r return r