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cores/uart/Stream2Wishbone: Add asserts on data_width/address_width.

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Florent Kermarrec 2022-04-20 11:01:21 +02:00
parent 5e451d68f7
commit ff6e7bd6ad
1 changed files with 2 additions and 0 deletions
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2
litex/soc/cores/uart.py
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@ -311,6 +311,8 @@ class Stream2Wishbone(Module):
self.wishbone = wishbone.Interface(data_width=data_width, adr_width=address_width) self.wishbone = wishbone.Interface(data_width=data_width, adr_width=address_width)
# # # # # #
assert data_width in [8, 16, 32]
assert address_width in [8, 16, 32]
cmd = Signal(8, reset_less=True) cmd = Signal(8, reset_less=True)
incr = Signal() incr = Signal()