cores/uart/Stream2Wishbone: Add asserts on data_width/address_width.

2025-01-04 09:52:26 -05:00 · 2022-04-20 11:01:21 +02:00 · 2022-04-20 11:01:21 +02:00 · ff6e7bd6ad
commit ff6e7bd6ad
parent 5e451d68f7
1 changed files with 2 additions and 0 deletions
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@ -311,6 +311,8 @@ class Stream2Wishbone(Module):
        self.wishbone = wishbone.Interface(data_width=data_width, adr_width=address_width)

        # # #
+        assert data_width    in [8, 16, 32]
+        assert address_width in [8, 16, 32]

        cmd              = Signal(8,                           reset_less=True)
        incr             = Signal()