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Bump the IRQ for liteeth based targets.

This commit is contained in:
Tim 'mithro' Ansell 2017-10-29 10:39:01 -07:00
parent 73e0036b99
commit ff72757b87
5 changed files with 5 additions and 5 deletions
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2
litex/boards/targets/arty.py
View File

@ -124,7 +124,7 @@ class MiniSoC(BaseSoC):
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
interrupt_map = { interrupt_map = {
"ethmac": 2, "ethmac": 3,
} }
interrupt_map.update(BaseSoC.interrupt_map) interrupt_map.update(BaseSoC.interrupt_map)

2
litex/boards/targets/kc705.py
View File

@ -104,7 +104,7 @@ class MiniSoC(BaseSoC):
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
interrupt_map = { interrupt_map = {
"ethmac": 2, "ethmac": 3,
} }
interrupt_map.update(BaseSoC.interrupt_map) interrupt_map.update(BaseSoC.interrupt_map)

2
litex/boards/targets/nexys_video.py
View File

@ -113,7 +113,7 @@ class MiniSoC(BaseSoC):
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
interrupt_map = { interrupt_map = {
"ethmac": 2, "ethmac": 3,
} }
interrupt_map.update(BaseSoC.interrupt_map) interrupt_map.update(BaseSoC.interrupt_map)

2
litex/boards/targets/sim.py
View File

@ -68,7 +68,7 @@ class MiniSoC(BaseSoC):
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
interrupt_map = { interrupt_map = {
"ethmac": 2, "ethmac": 3,
} }
interrupt_map.update(BaseSoC.interrupt_map) interrupt_map.update(BaseSoC.interrupt_map)

2
litex/boards/targets/simple.py
View File

@ -30,7 +30,7 @@ class MiniSoC(BaseSoC):
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
interrupt_map = { interrupt_map = {
"ethmac": 2, "ethmac": 3,
} }
interrupt_map.update(BaseSoC.interrupt_map) interrupt_map.update(BaseSoC.interrupt_map)