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litesata/example_designs: Add missing clock in phy instantiation

This commit is contained in:
Olof Kindgren 2015-06-26 01:15:34 +02:00
parent 125432b5b6
commit ffb6081720
1 changed files with 1 additions and 1 deletions
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2
misoclib/mem/litesata/example_designs/targets/core.py
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@ -17,7 +17,7 @@ class Core(Module):
self.clk_freq = clk_freq
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)