enjoy-digital 011773af8d Merge pull request #435 from enjoy-digital/spi_master_clk_divider ... soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…		2020-03-21 09:25:37 +01:00
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boards	targets: switch to add_ethernet method instead of EthernetSoC.	2020-03-20 23:46:15 +01:00
build	build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)	2020-03-09 19:02:23 +01:00
gen	gen/fhdl/verilog: fix signed init values	2020-01-12 22:06:35 +01:00
soc	Merge pull request #435 from enjoy-digital/spi_master_clk_divider	2020-03-21 09:25:37 +01:00
tools	litex_sim: add support for hybrid mac	2020-03-19 10:04:08 +01:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00