Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code ... it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.		2015-03-17 00:40:26 +01:00
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__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)	2013-12-10 23:32:12 +01:00
decorators.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
edif.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
module.py	fhdl/visit: fix TransformModule	2015-03-14 17:45:11 +01:00
namer.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
simplify.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
specials.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
std.py	fhdl/std: add FinalizeError import	2015-01-23 00:23:41 +08:00
structure.py	Raise exception when not using correct boolean operators	2014-10-27 19:40:22 +08:00
tools.py	fhdl/tools: do not attempt to rename sync clock domain if it does not exist	2014-11-21 14:51:05 -08:00
tracer.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
verilog.py	fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code	2015-03-17 00:40:26 +01:00
visit.py	fhdl/visit: fix TransformModule	2015-03-14 17:45:11 +01:00