Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code ... it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.		2015-03-17 00:40:26 +01:00
..
actorlib	move dma_lasmi to MiSoC	2015-03-02 08:23:02 +01:00
bank	bank: support direct mapping of CSRs on Wishbone	2014-11-30 22:28:39 +08:00
bus	move dfi/lasmibus/wishbone2lasmi to MiSoC sdram	2015-02-27 16:54:22 +01:00
fhdl	fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code	2015-03-17 00:40:26 +01:00
flow	endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)	2015-02-14 03:10:56 -08:00
genlib	migen/genlib/io: add DDRInput and DDROutput	2015-03-16 22:47:13 +01:00
sim	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
test	test/test_size: fix slice comparison	2014-11-03 12:08:43 +08:00
util	utils/misc: add gcd_multiple function to compute GCD or any number of integers	2013-12-12 17:36:50 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00