Florent Kermarrec bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu		2017-07-06 19:19:10 +02:00
..
cpu	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
code_8b10b.py	soc/cores: add code_8b10b from misoc	2017-04-19 11:05:21 +02:00
dna.py	soc/cores: dna/xadc: add missing copyright	2017-05-16 21:18:32 +02:00
frequency_meter.py	soc/core: add frequency meter	2017-06-01 00:39:19 +02:00
gpio.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
identifier.py	soc/cores/identifier: append 0 to contents to indicate end of string	2017-06-22 17:53:19 +02:00
nor_flash_16.py	soc/cores: move flash cores to cores directory	2017-04-19 10:58:15 +02:00
spi.py	soc/cores: add new spi master, remove obsolete one	2017-04-19 10:22:35 +02:00
spi_flash.py	soc/cores: move flash cores to cores directory	2017-04-19 10:58:15 +02:00
timer.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
uart.py	soc/core/uart: add UartStub to enable fast simulation with cpu	2017-07-06 19:19:10 +02:00
xadc.py	soc/cores: dna/xadc: add missing copyright	2017-05-16 21:18:32 +02:00