litex/examples
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
2012-02-15 16:30:16 +01:00
..
wb_intercon bus: simplify and cleanup 2012-02-15 16:30:16 +01:00
corelogic_conv.py Use meaningful class names 2012-01-20 23:07:32 +01:00
dataflow.py flow: simplify actor fragment interface 2012-01-10 15:54:51 +01:00
dataflow_dma.py actorlib/control: 'for' generator 2012-01-15 22:08:33 +01:00
fsm.py Use double quotes for all strings 2012-02-14 13:12:43 +01:00
lm32_inst.py Convert -> convert 2012-01-05 19:27:33 +01:00
memory.py fhdl: support memory read enable 2012-01-27 21:39:23 +01:00
simple_gpio.py bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00
using_record.py record: support aligned flattening 2012-01-09 19:16:11 +01:00