195 lines
12 KiB
Markdown
195 lines
12 KiB
Markdown
<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png"></p>
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```
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Copyright 2012-2022 / Enjoy-Digital & LiteX developers
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```
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[](https://github.com/enjoy-digital/litex/actions)
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# Welcome to LiteX!
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The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create [full FPGA based systems](https://github.com/enjoy-digital/litex/wiki/Projects).
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**Want to get started and/or looking for documentation? Make sure to visit the [Wiki](https://github.com/enjoy-digital/litex/wiki)!**
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**A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat]**.
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LiteX provides all the common components required to easily create an FPGA Core/SoC:
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- :heavy_check_mark: Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
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- :heavy_check_mark: Simple cores: RAM, ROM, Timer, UART, JTAG, etc….
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- :heavy_check_mark: Complex cores through the ecosystem of cores: [LiteDRAM](https://github.com/enjoy-digital/litedram), [LitePCIe](https://github.com/enjoy-digital/litepcie), [LiteEth](https://github.com/enjoy-digital/liteeth), [LiteSATA](https://github.com/enjoy-digital/litesata), etc...
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- :heavy_check_mark: Various CPUs & ISAs: RISC-V, OpenRISC, LM32, Zynq, X86 (through a PCIe), etc...
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- :heavy_check_mark: Mixed languages support with VHDL/Verilog/(n)Migen/Spinal-HDL/etc... integration capabilities.
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- :heavy_check_mark: Powerful debug infrastructure through the various [bridges](https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC) and [Litescope](https://github.com/enjoy-digital/litescope).
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- :heavy_check_mark: Direct/Fast simulation through [Verilator](https://www.veripool.org/verilator/).
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- :heavy_check_mark: Build backends for open-source and vendors toolchains.
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- :heavy_check_mark: And a lot more... :)
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By combining LiteX with the ecosystem of cores, creating complex SoCs becomes a lot easier than with traditional approaches while providing better portability and flexibility: Here is for example a Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA built and integrated with LiteX, running on a cheap repurposed [Acorn CLE215+ Mining Board](https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215):
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For more info, have a look at [Linux-on-LiteX-Vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project and try running Linux on your FPGA board!
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LiteX's digital logic is currently described with [Migen](https://github.com/m-labs/migen) which does not prevent users to create mixed language projects:
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- It's very common and easy to integrate VHDL/Verilog/SystemVerilog/nMigen/Spinal-HDL code in LiteX!
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- It's also very common to do the opposite and generate the LiteX design as a verilog file and integrate it in a traditional flow.
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LiteX was initially developed by [Enjoy-Digital](http://enjoy-digital.fr/) to create projects for clients (and we are still using it for that :)) and trying to take the different clients' requirements/needs consideration made, we think, the framework very flexible:
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- Some users only want to use it to easily interconnect their existing VHDL/Verilog/SV cores.
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- Some users are only interested to reuse the PCIe/Ethernet/SATA/etc cores as regular core and just integrate them in their traditional flow.
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- Some users with a hardware background start with the above approaches and then switch later to the full Python flow since find it more efficient.
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- Some users with a software background and fluent with Python start playing with FPGAs while they would probably never touch FPGA otherwise :)
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- Etc...
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We are well aware that everyone has a different background, so it's up to you to pick the right approach with LiteX that will be convenient for you!
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To get started we encourage you to read the [wiki](https://github.com/enjoy-digital/litex/wiki).
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You already have a FPGA board(s)? Visit [LiteX-Boards](https://github.com/litex-hub/litex-boards) to see if your board(s) is already supported!
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The framework is also far from perfect and we'll be happy to have your [feedback or/and contributions](https://github.com/enjoy-digital/litex/wiki/Feedback-Contribution-Support).
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Have fun! :wink:
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# Typical LiteX design flow:
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```
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+---------------+
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|FPGA toolchains|
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+----^-----+----+
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+--+-----v--+
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+-------+ | |
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| Migen +--------> |
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+-------+ | | Your design
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| LiteX +---> ready to be used!
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+----------------------+ | |
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|LiteX Cores Ecosystem +--> |
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+----------------------+ +-^-------^-+
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(Eth, SATA, DRAM, USB, | |
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PCIe, Video, etc...) + +
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board target
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file file
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```
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LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:
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| Name | Build Status | Description |
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| ------------------------------------------------------------ | ---------------------------------------------------------------------------------------------------------------------------------- | ------------------------- |
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| [LiteX-Boards](http://github.com/litex-hub/litex-boards) | [](https://github.com/litex-hub/litex-boards/actions) | Boards support |
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| [LiteDRAM](http://github.com/enjoy-digital/litedram) | [](https://github.com/enjoy-digital/litedram/actions) | DRAM |
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| [LiteEth](http://github.com/enjoy-digital/liteeth) | [](https://github.com/enjoy-digital/liteeth/actions) | Ethernet |
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| [LitePCIe](http://github.com/enjoy-digital/litepcie) | [](https://github.com/enjoy-digital/litepcie/actions) | PCIe |
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| [LiteSATA](http://github.com/enjoy-digital/litesata) | [](https://github.com/enjoy-digital/litesata/actions) | SATA |
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| [LiteSDCard](http://github.com/enjoy-digital/litesdcard) | [](https://github.com/enjoy-digital/litesdcard/actions) | SD card |
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| [LiteICLink](http://github.com/enjoy-digital/liteiclink) | [](https://github.com/enjoy-digital/liteiclink/actions) | Inter-Chip communication |
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| [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [](https://github.com/enjoy-digital/litejesd204b/actions) | JESD204B |
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| [LiteSPI](http://github.com/litex-hub/litespi) | [](https://github.com/litex-hub/litespi/actions) | SPI/SPIFlah |
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| [LiteHyperBus](http://github.com/litex-hub/litehyperbus) | [](https://github.com/litex-hub/litehyperbus/actions) | HyperBus/HyperRam |
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| [LiteScope](http://github.com/enjoy-digital/litescope) | [](https://github.com/enjoy-digital/litescope/actions) | Logic analyzer |
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# Examples of designs built with LiteX:
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Custom PCIe SDI Capture/Playback board built around LitePCIe and integrated with LiteX, allowing full control of the SDI flow and very low latency.
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Alternative firmware/gateware for the SDS1104X-E Scope:
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HBM2 test infrastructure on Forest Kitten 33:
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To discover more products/projects built with LiteX, visit the [projects page](https://github.com/enjoy-digital/litex/wiki/Projects) on the Wiki.
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# Papers, Presentations, Tutorials, Links
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**FPGA lessons/tutorials:**
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- https://github.com/enjoy-digital/fpga_101
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**Migen tutorial:**
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- https://m-labs.hk/migen/manual
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**OSDA 2019 paper/slides:**
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- https://osda.gitlab.io/19/1.1.pdf
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- https://osda.gitlab.io/19/1.1-slides.pdf
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**Linux on LiteX-Vexriscv:**
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- https://github.com/litex-hub/linux-on-litex-vexriscv
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**RISC-V Getting Started Guide:**
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- https://risc-v-getting-started-guide.readthedocs.io/en/latest/
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**LiteX vs. Vivado First Impressions:**
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- https://www.bunniestudios.com/blog/?p=5018
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**35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
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- https://www.youtube.com/watch?v=AlmVxR0417c
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**Tim has to many projects - LatchUp Edition:**
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https://www.youtube.com/watch?v=v7WrTmexod0
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# Sub-packages
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**litex.gen**
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Provides specific or experimental modules to generate HDL that are not integrated in Migen.
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**litex.build:**
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Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
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**litex.soc:**
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Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
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# Quick start guide
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1. Install Python 3.6+ and FPGA vendor's development tools and/or [Verilator](http://www.veripool.org/).
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2. Install Migen/LiteX and the LiteX's cores:
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```sh
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$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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$ chmod +x litex_setup.py
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$ ./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)
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```
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Later, if you need to update all repositories:
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```sh
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$ ./litex_setup.py --update
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```
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> **Note:** On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
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> **Note:** On Windows, it's possible you'll have to set `SHELL` environment variable to `SHELL=cmd.exe`.
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3. Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):
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```sh
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$ pip3 install meson ninja
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$ ./litex_setup.py --gcc=riscv
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```
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4. Build the target of your board...:
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Go to litex-boards/litex_boards/targets and execute the target you want to build.
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5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX directly on your computer without any FPGA board:
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On Linux (Ubuntu):
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```sh
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$ sudo apt install libevent-dev libjson-c-dev verilator
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$ litex_sim --cpu-type=vexriscv
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```
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On MacOS:
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```sh
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$ brew install json-c verilator libevent
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$ brew cask install tuntap
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$ litex_sim --cpu-type=vexriscv
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```
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6. Run a terminal program on the board's serial port at 115200 8-N-1.
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You should get the BIOS prompt like the one below.
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<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
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# Community
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<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex-hub.png" width="400"></p>
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Over the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found at https://github.com/litex-hub.
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# Contact
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E-mail: florent@enjoy-digital.fr
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