Sébastien Bourdeauducq 07efe9d7b1 Merge pull request #31 from burnpanck/fix-value_bits_sign-mul ... fix bug in value_bits_sign of mul operatiors		2015-09-10 10:25:57 -07:00
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actorlib	migen/actorlib/packet: fix source.error in Depacketizer	2015-08-19 01:12:07 +02:00
bank	AutoCSR: refactor common gatherer code	2015-09-06 20:00:14 -07:00
bus	bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)	2015-06-19 08:37:16 +02:00
fhdl	fixed bug in value_bits_sign of mul operatiors	2015-09-09 15:32:09 +02:00
flow	migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active)	2015-08-09 19:54:38 +02:00
genlib	migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)	2015-06-02 19:26:42 +02:00
sim	vpi: cleanup (thanks sb)	2015-05-13 10:13:14 +02:00
test	add examples tests	2015-05-01 00:50:17 +08:00
util	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00