07efe9d7b1
Merge pull request #31 from burnpanck/fix-value_bits_sign-mul
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fix bug in value_bits_sign of mul operatiors
2015-09-10 10:25:57 -07:00
6e9d6d7a8e
fixed bug in value_bits_sign of mul operatiors
2015-09-09 15:32:09 +02:00
94a2499ce5
AutoCSR: refactor common gatherer code
2015-09-06 20:00:14 -07:00
5253b0c06e
migen/actorlib/packet: fix source.error in Depacketizer
2015-08-19 01:12:07 +02:00
646667213e
migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active)
2015-08-09 19:54:38 +02:00
f32f9be17a
resetless -> reset_less
2015-07-27 11:46:11 +08:00
cc6877df9e
fhdl: allow use of ResetSignal() on resetless clock domains
2015-07-27 01:51:52 +08:00
5a535ef347
Revert "migen/actorlib/fifo: add FIFO wrapper function"
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This reverts commit d0a19c4be8
2015-07-24 19:25:36 +08:00
d0a19c4be8
migen/actorlib/fifo: add FIFO wrapper function
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Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
2015-07-24 13:02:54 +02:00
1f1ff5a5e9
migen/fhdl/tools: fix rename_clock_domain when new == old
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Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
5713ae381a
actorlib/packet/Depacketizer: manage layouts without error signal
2015-07-22 21:43:21 +02:00
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
71627cf9f0
bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
2015-06-19 08:37:16 +02:00
f8b1152b98
wishbone: add Cache (from WB2LASMI)
2015-06-17 15:31:49 +02:00
33b536e505
migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter)
2015-06-02 19:29:38 +02:00
79624ce849
migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)
2015-06-02 19:26:42 +02:00
fd16b66bdf
genlib/cdc: add BusSynchronizer
2015-06-02 17:40:42 +08:00
a5f495aeac
fhdl/verilog: add reserved keywords
2015-05-23 14:01:08 +02:00
9cabcf14e9
migen/genlib/record: add leave_out parameter to connect
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Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00
f6624b34f0
migen/actorlib/spi: apply missing CSR renaming
2015-05-13 10:17:31 +02:00
76302d7aa6
vpi: cleanup (thanks sb)
2015-05-13 10:13:14 +02:00
98cf103c65
vpi: fix and simplify windows simulation (ends of msg were ignored)
2015-05-13 03:03:34 +02:00
88a406ebec
migen/genlib/misc: replace Timeout with WaitTimer from artiq
2015-05-12 16:14:58 +02:00
fe6eef7069
Windows simulation support
2015-05-09 21:09:52 +08:00
96bff77c36
add examples tests
2015-05-01 00:50:17 +08:00
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
0da9311d70
migen/genlib: avoid use of floating point in reverse_bytes
2015-04-27 21:04:18 +02:00
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
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BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
7ec0ecae11
test: add test for asic_syntax
2015-04-22 12:29:07 +08:00
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
d83e170872
global: more pep8
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we will have to continue the work... volunteers are welcome :)
2015-04-13 21:33:44 +02:00
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
a2c17cdcef
Merge branch 'master' of https://github.com/m-labs/migen
2015-04-13 09:37:03 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
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We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
Sébastien Bourdeauducq
Yves Delley
Robert Jordens
Florent Kermarrec
William D. Jones
Alain Péteut
Guy Hutchison