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Dolu1990-patch-1
allows_clk_name_override
ci-cpus
ci-cva6
ci-dev-test
ci-openrisc
ctu-can-fd
dma_nax
efinix_fixes
efinix_fixes2
export_csr_c_rework
framebuffer_change
generic_toolchain
ghdl_fix
gowin_emcu_uart
hyperbus_2x
hyperbus_io_regs
hyperbus_variable_latency
hyperram_decoupling
hyperram_new
kianv
liteeth_wishbone_tx_rx_buses
master
multi-channel-pwm
naxriscv-merge
naxriscv_update
neorv32_litex_wrapper
neorv32_params
usb_ohci_phy_fix
verilog_improvements
verilog_improvements_2
vexriscv_smp_irqs
video_framebuffer_skip_first_frame
video_mod_fix
wishbone_dma_ctrl
wishbone_word_byte_addressing
zynqmp_aximaster_eth_i2c_uart
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2020.04
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2024.04
Select branches
Hide Pull Requests
Dolu1990-patch-1
allows_clk_name_override
ci-cpus
ci-cva6
ci-dev-test
ci-openrisc
ctu-can-fd
dma_nax
efinix_fixes
efinix_fixes2
export_csr_c_rework
framebuffer_change
generic_toolchain
ghdl_fix
gowin_emcu_uart
hyperbus_2x
hyperbus_io_regs
hyperbus_variable_latency
hyperram_decoupling
hyperram_new
kianv
liteeth_wishbone_tx_rx_buses
master
multi-channel-pwm
naxriscv-merge
naxriscv_update
neorv32_litex_wrapper
neorv32_params
usb_ohci_phy_fix
verilog_improvements
verilog_improvements_2
vexriscv_smp_irqs
video_framebuffer_skip_first_frame
video_mod_fix
wishbone_dma_ctrl
wishbone_word_byte_addressing
zynqmp_aximaster_eth_i2c_uart
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2020.04
2020.08
2020.12
2021.04
2021.08
2021.12
2022.04
2022.08
2022.12
2023.04
2023.08
2023.12
2024.04
-
9007562264
2db93c8e78
intoa1a3e846ac
Dolu1990
2024-09-06 16:07:17 +0200 -
2db93c8e78
core/vexiiriscv: improve l2 timings
Dolu1990
2024-09-06 16:05:34 +0200 -
e93fc354bd
6f0b39772a
intoa1a3e846ac
AndrewD
2024-09-06 12:49:16 +0200 -
a9744b5fe5
e19dfa8800
intoa1a3e846ac
AndrewD
2024-09-06 08:46:56 +0200 -
a0fc14b8b8
599c6dde37
intoa1a3e846ac
Dolu1990
2024-09-06 08:46:56 +0200 -
9b9acaada9
3a6b7b2246
intoa1a3e846ac
Fin Maaß
2024-09-06 08:32:24 +0200 -
a1a3e846ac
enjoy-digital
2024-09-06 08:32:11 +0200 -
f048896d30
434c0f8447
intoe62d84b77b
sergpolkin
2024-09-05 12:37:08 -0400 -
acf74d0f71
ac871c690c
intoe62d84b77b
jdavidberger
2024-09-05 17:43:53 +0200 -
bd03c496a1
bios: add spiram
Fin Maaß
2024-09-05 12:02:28 +0200 -
599c6dde37
Dolu1990
2024-09-05 16:12:32 +0200 -
4bedb4ff17
531cf82bdd
intoe62d84b77b
hhe07
2024-09-05 16:01:16 +0200 -
c0fddb6561
build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled
Dolu1990
2024-09-05 15:21:12 +0200 -
642cfbe9a7
soc/cores/vexiiriscv: update clocks + add video framebuffer support
Dolu1990
2024-09-05 15:16:15 +0200 -
e62d84b77b
Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support"
Dolu1990
2024-09-05 15:15:49 +0200 -
0ea6dd91aa
soc/cores/vexiiriscv: update clocks + add video framebuffer support
Dolu1990
2024-09-05 15:13:35 +0200 -
fa47c62b6d
enjoy-digital
2024-09-05 14:40:34 +0200 -
f512c65077
vexiiriscv git update
Dolu1990
2024-09-05 13:17:22 +0200 -
2190ca403a
core/usb_ohci: fix SDRTristate clock
Dolu1990
2024-09-05 10:17:22 +0200 -
f67b39739e
soc/integration/add_ethernet: Expose full_memory_we parameter.
Florent Kermarrec
2024-09-05 10:18:12 +0200 -
1f2418de3b
core/usb_ohci: fix SDRTristate clock
usb_ohci_phy_fix
Dolu1990
2024-09-05 10:17:22 +0200 -
84e7e816c7
efinix: pll now force the generated clock into cd.clk *WARNING*
Dolu1990
2024-09-05 10:16:43 +0200 -
d3161ad74c
build/efinix/platform: fix get_pin_name()
Andrew Dennison
2024-02-26 03:32:50 +0000 -
eda553aeaa
enjoy-digital
2024-09-03 17:54:27 +0200 -
d0215001f4
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
Gwenhael Goavec-Merou
2024-09-03 17:47:40 +0200 -
a90ab9dcca
efinix: Merge pt.sdc to the litex sdc to get constraints right
Dolu1990
2024-09-03 12:05:26 +0200 -
dc29b6f4e5
CHANGES.md: Update.
Florent Kermarrec
2024-09-03 09:43:29 +0200 -
4152d22065
Revert "build/efinix/platform: fix get_pin_name()"
Gwenhael Goavec-Merou
2024-09-03 08:51:39 +0200 -
3de5832b9c
vexiiriscv: Now use pll.locked for debug reset
Dolu1990
2024-09-03 07:58:24 +0200 -
19b3f24d9f
efinix: ifacewriter support drive strength and slew
Dolu1990
2024-09-03 07:57:30 +0200 -
e01ce6f948
efinix: ifacewriter support drive strength and slew
Dolu1990
2024-09-03 07:55:25 +0200 -
3bdbe1ebcf
CHANGES.md: Update.
Florent Kermarrec
2024-09-02 14:20:09 +0200 -
af0dc7f98b
enjoy-digital
2024-09-02 14:08:07 +0200 -
60e6f1f792
ccbfce920a
into15cd556750
David A Roberts
2024-09-02 11:34:45 +0200 -
babe233407
build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software)
Gwenhael Goavec-Merou
2024-09-01 09:55:01 +0200 -
3da470048a
build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model
Gwenhael Goavec-Merou
2024-09-01 09:53:24 +0200 -
658774c965
222848298f
into15cd556750
AndrewD
2024-08-31 17:26:52 -0400 -
768fb6fd29
a47bbb28f5
into15cd556750
Joshua Wise
2024-08-31 17:26:21 -0400 -
2f2b292e06
vexii add with-cpu-clk
Dolu1990
2024-08-30 18:16:56 +0200 -
15cd556750
enjoy-digital
2024-08-30 15:38:59 +0200 -
61b54aa491
soc/integration/soc: Fix add_peripheral.
Florent Kermarrec
2024-08-30 12:08:00 +0200 -
c554752e8a
soc/cores/hyperbus: Add automatic read burst detection.
hyperram_new
Florent Kermarrec
2024-08-29 19:39:56 +0200 -
c14f1d0816
vexiiriscv add video support
Dolu1990
2024-08-30 10:44:36 +0200 -
5fb873d209
efinix: Add support for more IO
Dolu1990
2024-08-30 10:44:10 +0200 -
3bde3e9848
soc/cores/hyperbus: Add automatic write burst detection.
Florent Kermarrec
2024-08-29 16:24:12 +0200 -
11be91621e
cd3364a433
into4ded509444
AndrewD
2024-08-29 14:03:23 +0200 -
b2e26bd32d
91ec2d5e3b
into4ded509444
Rowan Goemans
2024-08-29 14:03:14 +0200 -
fac80c3a51
soc/cores/hyperbus: Full rewrite of HyperRAM core.
Florent Kermarrec
2024-08-26 11:24:16 +0200 -
cc3f13670a
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
Dolu1990
2024-08-28 20:13:03 +0200 -
d4003b8cfa
efinix add SCHMITT_TRIGGER support
Dolu1990
2024-08-28 19:59:30 +0200 -
00bee07831
bb2284b40b
into4ded509444
Dmitry
2024-08-28 17:42:35 +0200 -
a925773205
715098f2f1
into4ded509444
AndrewD
2024-08-28 17:38:26 +0200 -
fe2846a5b3
af19e210aa
into4ded509444
Jiaxun Yang
2024-08-27 20:58:35 +0100 -
d93e0942d6
4276a181ba
into4ded509444
Andrew E Wilson
2024-08-27 12:54:15 -0500 -
4ded509444
Gwenhael Goavec-Merou
2024-08-27 09:50:04 +0200 -
f8feb8a192
Gwenhael Goavec-Merou
2024-08-27 09:49:15 +0200 -
6d46a5ba05
efinix: Fix PLL with external clock input ifacewriter
Dolu1990
2024-08-27 09:02:58 +0200 -
0fcc27f58f
build/colognechip/colognechip.py: simplify constrains file with the new toolchain
Gwenhael Goavec-Merou
2024-08-24 12:20:19 +0200 -
07e11858c6
soc/cores/clock/colognechip.py: rework/fix locked signal
Gwenhael Goavec-Merou
2024-08-24 12:19:34 +0200 -
ef775e0b8e
Gwenhael Goavec-Merou
2024-08-24 10:37:17 +0200 -
ac871c690c
Merge remote-tracking branch 'origin/master' into feature/mode_based_bus_crossbar
Justin Berger
2024-08-23 16:42:23 -0600 -
0be8d98154
Add timeout to wb crossbar
Justin Berger
2024-08-23 16:38:25 -0600 -
afce6a6887
f39bc44f3f
into6d0ae25d65
Joseph Faye
2024-08-23 11:19:52 +0200 -
c857f7845e
soc/cores/hyperbus/HyperRAMPHY: Add specific sampling clk_domain.
hyperram_decoupling
Florent Kermarrec
2024-08-22 19:53:45 +0200 -
c09d57d52d
soc/cores/hyperbus: Minor cleanups.
Florent Kermarrec
2024-08-22 17:36:47 +0200 -
3213cf8f84
soc/cores/hyperbus: Generate shift signal from HyperRAMPHY.
Florent Kermarrec
2024-08-22 17:20:54 +0200 -
0edcd2da0e
soc/cores/hyperbus: Cleanup Shift-Register and rename signals.
Florent Kermarrec
2024-08-22 17:07:06 +0200 -
2dd7e3b9b3
soc/cores/hyperbus: Shorten reg signals and use common done for read/write register accesses.
Florent Kermarrec
2024-08-22 16:39:30 +0200 -
19f47aa317
soc/cores/hyperbus: Directly drive phy.cs.
Florent Kermarrec
2024-08-22 16:31:52 +0200 -
120715a3d1
soc/cores/hyperbus: Cleanup parameters.
Florent Kermarrec
2024-08-22 16:23:03 +0200 -
b9210e7553
soc/cores/hyperbus: Also move ClkGen to HyperRAMPHY.
Florent Kermarrec
2024-08-22 16:03:55 +0200 -
4400fbb966
Apicula: add GWINR-18 aliases
Pepijn de Vos
2024-08-22 16:02:41 +0200 -
4f0efc2b25
soc/cores/hyperbus: Add HyperRAMPHY and move related logic to it.
Florent Kermarrec
2024-08-22 15:16:33 +0200 -
f54ecfa5ff
soc/cores/hyperbus: Avoid setting sr directly in FSM, use sr_load/sr_load_value.
Florent Kermarrec
2024-08-22 14:49:55 +0200 -
7eb9fa81df
592f6a10dc
into6d0ae25d65
Jevin Sweval
2024-08-21 15:51:19 -0400 -
61d072945d
32dc99ebe0
into6d0ae25d65
Jevin Sweval
2024-08-21 15:51:19 -0400 -
98663f83fc
260577cae8
into6d0ae25d65
Jevin Sweval
2024-08-21 15:51:19 -0400 -
6d0ae25d65
enjoy-digital
2024-08-21 19:25:41 +0200 -
a88cee70c8
test/test_hyperbus: Update.
hyperbus_2x
Florent Kermarrec
2024-08-21 17:10:44 +0200 -
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
Florent Kermarrec
2024-08-21 17:10:36 +0200 -
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
Florent Kermarrec
2024-08-21 15:35:21 +0200 -
5587f5954d
test/test_hyperbus: Add 2:1 test.
Florent Kermarrec
2024-08-21 15:00:11 +0200 -
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
Florent Kermarrec
2024-08-21 12:07:55 +0200 -
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
Florent Kermarrec
2024-08-21 11:50:46 +0200 -
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
Florent Kermarrec
2024-08-21 11:41:13 +0200 -
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
Florent Kermarrec
2024-08-21 11:17:55 +0200 -
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
Florent Kermarrec
2024-08-21 10:57:36 +0200 -
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
Florent Kermarrec
2024-08-20 22:05:38 +0200 -
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
Florent Kermarrec
2024-08-20 21:54:15 +0200 -
298a004f08
enjoy-digital
2024-08-20 19:47:01 +0200 -
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
hyperbus_io_regs
Florent Kermarrec
2024-08-20 17:11:02 +0200 -
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
Florent Kermarrec
2024-08-20 16:19:15 +0200 -
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
Florent Kermarrec
2024-08-20 15:44:37 +0200 -
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
Florent Kermarrec
2024-08-20 15:26:26 +0200 -
47e7441881
019b143854
intob7605bc633
AndrewD
2024-08-20 23:21:01 +1000 -
76cf004913
test/test_hyperbus: Update.
Florent Kermarrec
2024-08-20 15:17:36 +0200 -
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
Florent Kermarrec
2024-08-20 14:58:51 +0200 -
3a6b7b2246
core: i2c: add i2c master
Fin Maaß
2024-07-26 16:18:02 +0200 -
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
Florent Kermarrec
2024-08-20 14:44:33 +0200 -
b7605bc633
enjoy-digital
2024-08-20 14:29:35 +0200