Florent Kermarrec 0c687bc29e soc/interconnect/stream: add support for buffered async fifo		2018-12-08 01:24:08 +01:00
..
cores	cores/clock: test and fix ECP5PLL, phase still not implemented.	2018-11-27 17:24:22 +01:00
integration	soc/integration/soc_core: add csr_map_update function	2018-11-21 08:39:52 +01:00
interconnect	soc/interconnect/stream: add support for buffered async fifo	2018-12-08 01:24:08 +01:00
software	bios/sdram: flush l2 cache only when present	2018-11-26 18:37:45 +01:00
tools	create utils directory and move the litex utils to it	2018-11-16 14:37:19 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00