Gwenhael Goavec-Merou 0d1d378966 soc/cores/cpu/zynqmp/core.py: added interrupts support		2024-06-18 10:59:42 +02:00
..
build	build/vhd2v_converter: Add GHDL synth woraround.	2024-06-14 11:25:21 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	litex/gen/common: Add short and long byte size definitions.	2024-06-13 09:54:20 +02:00
soc	soc/cores/cpu/zynqmp/core.py: added interrupts support	2024-06-18 10:59:42 +02:00
tools	litex_json2dts_linux: Cleanup bootargs IP address generation.	2024-06-13 12:14:44 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00