Florent Kermarrec 0e7d8219ea soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate. ... Ex of instance: from litex.soc.cores import gpio gpio_in_pads = Signal(16) self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True) self.add_csr("gpio_in")		2021-03-09 13:57:48 +01:00
..
build	build/radiant: Skip location constraint for X pins	2021-03-08 14:27:32 +00:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate.	2021-03-09 13:57:48 +01:00
tools	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00