Florent Kermarrec 0f8f89a269 update clock constraints for SATA1 and use sys_clk of 200MHz ... - data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...		2014-12-17 19:24:23 +01:00
..
command	command: fix ValueError msg	2014-12-15 15:34:00 +01:00
link	link_tb: fix cont regression	2014-12-15 20:00:19 +01:00
phy/k7sataphy	update clock constraints for SATA1 and use sys_clk of 200MHz	2014-12-17 19:24:23 +01:00
test	improve check function	2014-12-17 08:58:02 +01:00
transport	move Counter to common and use it in all modules	2014-12-15 19:33:38 +01:00
__init__.py	bist: add count to bist parameters	2014-12-15 19:48:22 +01:00
bist.py	bist: add count to bist parameters	2014-12-15 19:48:22 +01:00
common.py	move Counter to common and use it in all modules	2014-12-15 19:33:38 +01:00