litex/misoclib/mem/litesata/example_designs
2015-02-28 21:45:05 +01:00
..
platforms liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
targets remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
test litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
make.py liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00