Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv		2015-02-28 21:45:05 +01:00
..
targets	remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)	2015-02-28 11:36:15 +01:00
test	litescope: create example_designs directory	2015-02-28 10:42:12 +01:00
make.py	liteXXX cores: remove redefinition of get_csr_csv	2015-02-28 21:45:05 +01:00