litex/litex/tools
2020-11-12 14:45:46 +01:00
..
remote tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4). 2020-11-09 16:36:04 +01:00
__init__.py tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00
litex_client.py tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. 2020-10-22 17:45:45 +02:00
litex_crossover_uart.py tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
litex_gen.py tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
litex_json2dts.py tools/litex_json2dts: fix missing {. 2020-11-12 14:45:46 +01:00
litex_jtag_uart.py tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
litex_read_verilog.py tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
litex_server.py tools/litex_server: revert CommUDP's max length to 1 (needs more testing). 2020-11-09 16:35:04 +01:00
litex_sim.py tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki). 2020-11-06 12:49:43 +01:00
litex_term.py tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00