litex/litex/soc
2019-10-10 21:35:06 +02:00
..
cores cpu: add buses list and use it in soc_core to add bus masters 2019-10-10 21:35:06 +02:00
integration cpu: add buses list and use it in soc_core to add bus masters 2019-10-10 21:35:06 +02:00
interconnect soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00
software bios/main: use same banner than README (MiSoC cited in README/LICENSE) 2019-10-10 19:21:32 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00