litex/litex/soc/cores
2019-10-10 21:35:06 +02:00
..
cpu cpu: add buses list and use it in soc_core to add bus masters 2019-10-10 21:35:06 +02:00
__init__.py
bitbang.py soc/cores/bitbang: use new CSRField (no functional change) 2019-09-16 16:56:00 +02:00
clock.py soc/cores/clocks: improve readibility 2019-09-29 15:58:22 +02:00
code_8b10b.py
dna.py
ecc.py soc/cores/ecc: improve readibility, uniformize with others cores 2019-09-29 16:02:04 +02:00
freqmeter.py soc/cores: rename frequency_meter to freqmeter and uniformize with others cores 2019-09-29 16:08:39 +02:00
gpio.py soc/cores/gpio: uniformize with others cores 2019-09-29 16:10:44 +02:00
hyperbus.py
icap.py fix comments 2019-10-06 10:47:28 +02:00
identifier.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
jtag.py soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) 2019-09-06 11:55:41 +02:00
prbs.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
pwm.py
spi.py soc/cores/spi: use new CSRField (no functional change) 2019-09-16 17:02:55 +02:00
spi_flash.py spi_flash: document register fields 2019-09-20 12:42:43 +08:00
timer.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
uart.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
up5kspram.py
usb_fifo.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
xadc.py soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00