91 lines
2.7 KiB
Python
91 lines
2.7 KiB
Python
import unittest
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import os
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from migen import *
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from litex.soc.integration.builder import *
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def build_test(socs):
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errors = 0
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for soc in socs:
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os.system("rm -rf build")
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builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
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builder.build()
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errors += not os.path.isfile("./build/gateware/top.v")
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os.system("rm -rf build")
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return errors
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class TestTargets(unittest.TestCase):
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# altera boards
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def test_de0nano(self):
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from litex.boards.targets.de0nano import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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# xilinx boards
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def test_minispartan6(self):
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from litex.boards.targets.minispartan6 import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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def test_arty(self):
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from litex.boards.targets.arty import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_nexys4ddr(self):
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from litex.boards.targets.nexys4ddr import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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def test_nexys_video(self):
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from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_genesys2(self):
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from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_kc705(self):
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from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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# lattice boards
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def test_versa_ecp5(self):
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from litex.boards.targets.versa_ecp5 import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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def test_versa_ulx3s(self):
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from litex.boards.targets.ulx3s import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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# build simple design for all platforms
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def test_simple(self):
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platforms = [
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"arty",
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"de0nano",
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"genesys2",
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"kc705",
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"kcu105",
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"machxo3",
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"minispartan6",
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"nexys4ddr",
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"nexys_video",
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"tinyfpga_bx",
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"versa_ecp3",
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"versa_ecp5"
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]
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for p in platforms:
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os.system("litex/boards/targets/simple.py litex.boards.platforms." + p +
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" --cpu-type=vexriscv " +
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" --no-compile-software " +
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" --no-compile-gateware " +
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" --uart-stub=True")
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