Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU ... VexRiscv can now replace LM32 for almost all usecases and we now have better software support with RISC-V.		2019-04-22 09:41:07 +02:00
..
__init__.py	add test directory with test_code_8b10b.py (from misoc)	2017-04-24 18:46:55 +02:00
test_axi.py	soc/interconnect/axi: add AXIBurst2Beat	2019-04-19 12:13:16 +02:00
test_axi_lite.py	test: remove waveforms generation	2019-04-22 08:41:28 +02:00
test_code_8b10b.py	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
test_csr.py	test: add basic test_csr	2019-02-27 21:46:00 +01:00
test_gearbox.py	test: remove waveforms generation	2019-04-22 08:41:28 +02:00
test_targets.py	global: switch to VexRiscv as the default CPU	2019-04-22 09:41:07 +02:00