Florent Kermarrec 10dd55fd88 boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter		2018-07-18 11:51:58 +02:00
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boards	boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter	2018-07-18 11:51:58 +02:00
build	build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)	2018-05-01 12:02:54 +02:00
gen	build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)	2018-05-01 12:02:54 +02:00
soc	software/bios/linker: revert data section since required by RISC-V compiler	2018-07-18 09:30:14 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00