Sebastien Bourdeauducq 5183774ec8 bus/wishbone2asmi: do not use MemoryPort		2012-11-26 19:14:59 +01:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	bus/asmibus: swap port position to be consistent with wishbone API	2012-11-17 19:42:39 +01:00
csr.py	bus/csr: allow specifying existing interface	2012-11-17 19:44:25 +01:00
dfi.py	bus/dfi: reset active low signals to 1	2012-04-01 17:43:24 +02:00
memory.py	bus: memory initiator	2012-11-23 16:22:50 +01:00
simple.py	bus: add interconnect statements function	2012-02-17 23:51:32 +01:00
transactions.py	bus/transactions: add busname parameter	2012-11-17 19:36:08 +01:00
wishbone.py	bus/wishbone: allow specifying existing interface	2012-11-17 19:42:06 +01:00
wishbone2asmi.py	bus/wishbone2asmi: do not use MemoryPort	2012-11-26 19:14:59 +01:00
wishbone2csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00