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altera
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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anlogic
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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efinix
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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gowin
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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lattice
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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microsemi
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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osfpga
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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quicklogic
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build/generic_platform build/xxx/platform soc/integration/builder:
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2023-03-04 11:36:29 +01:00 |
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sim
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Merge pull request #1638 from gatecat/jtagremote_fix
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2023-03-08 18:47:52 +01:00 |
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xilinx
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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__init__.py
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dfu.py
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generic_platform.py
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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generic_programmer.py
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build: Cosmetic cleanups.
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2022-08-05 08:22:36 +02:00 |
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generic_toolchain.py
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build/xx/toolchains: allows override clock naming
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2023-08-31 15:18:15 +02:00 |
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io.py
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build/io: Allow passing clk as str on DDRInput/Output, wrap DDROutput IOs and minor ident fixes.
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2023-08-30 10:52:13 +02:00 |
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nextpnr_wrapper.py
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build/nextpnr_wrapper,yosys_nextpnr_toolchain,yosys_wrapper: fix LF for windows (#1536)
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2022-12-14 22:04:40 +01:00 |
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openfpgaloader.py
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build/openfpgaloader: support --fpga-part
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2023-06-06 10:02:25 +02:00 |
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openocd.py
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build: Cosmetic cleanups.
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2022-08-05 08:22:36 +02:00 |
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parser.py
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build/parser: adding a fallback to search for a platform explicitly into litex-boards package when platform name isn't found
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2023-01-11 18:33:48 +01:00 |
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tools.py
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vhd2v_converter.py
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vhd2v: Use GHDL directly
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2022-10-29 22:27:23 +10:30 |
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yosys_nextpnr_toolchain.py
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yosys: add command line arg to be quiet
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2023-06-06 08:51:22 +02:00 |
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yosys_wrapper.py
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yosys: add command line arg to be quiet
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2023-06-06 08:51:22 +02:00 |
