litex/misoclib/mem/litesata/example_designs/targets
Florent Kermarrec 1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
..
__init__.py liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
bist.py litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data). 2015-05-01 17:51:18 +02:00
core.py litesata: pep8 (E302) 2015-04-13 15:12:39 +02:00