1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
c8bcbfb855
litesata: pep8 (E261, E271)
2015-04-13 15:51:17 +02:00
d0c5bd377a
litesata: pep8 (E302)
2015-04-13 15:12:39 +02:00
808e1fe866
litesata: pep8 (replace tabs with spaces)
2015-04-13 14:59:00 +02:00
6e2a662dd7
litesata: adapt to new SoC API
2015-04-01 17:37:53 +08:00
649cdeb265
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
9e01bf5fdd
litesata: create example design derived from SoC
2015-03-01 11:33:38 +01:00
c21a7956c8
liteXXX cores: remove Identifier duplication
2015-03-01 11:24:58 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
0dfca49e68
litesata: move file and modify import to misoclib.mem.litesata
2015-02-28 11:03:24 +01:00
Florent Kermarrec
Sebastien Bourdeauducq