Sebastien Bourdeauducq 140ddd31a4 mixxeo: add DVI output pins		2013-09-17 18:14:41 +02:00
..
platforms	mixxeo: add DVI output pins	2013-09-17 18:14:41 +02:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	altera_quartus: fix import _Fragment	2013-08-26 20:13:30 +02:00
crg.py	Use migen.fhdl.std	2013-05-26 18:07:26 +02:00
generic_platform.py	add mist synthesis mode to build	2013-08-12 13:13:25 +02:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	add mist synthesis mode to build	2013-08-12 13:13:25 +02:00