Sebastien Bourdeauducq 398ece8fe2 fhdl/verilog: add option to display which comb blocks are run ... This is a debug hack to help find combinatorial loops in designs.		2012-04-30 16:38:40 -05:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	fhdl: register memory objects with namespace	2012-03-06 18:33:44 +01:00
structure.py	fhdl: support len() on signals	2012-04-08 18:06:22 +02:00
tools.py	fhdl: support forwarding of bidirectional signals from instance ports	2012-02-16 18:34:32 +01:00
tracer.py	fhdl: register memory objects with namespace	2012-03-06 18:33:44 +01:00
verilog.py	fhdl/verilog: add option to display which comb blocks are run	2012-04-30 16:38:40 -05:00
verilog_mem_behavioral.py	fhdl: register memory objects with namespace	2012-03-06 18:33:44 +01:00