65 lines
2.2 KiB
Python
65 lines
2.2 KiB
Python
from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.test.common import *
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from misoclib.com.litepcie.test.model.phy import PHY
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from misoclib.com.litepcie.test.model.tlp import *
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from misoclib.com.litepcie.test.model.chipset import Chipset
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def print_host(s):
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print_with_prefix(s, "[HOST] ")
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# Host model
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class Host(Module):
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def __init__(self, dw, root_id, endpoint_id, bar0_size=1*MB,
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phy_debug=False,
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chipset_debug=False, chipset_split=False, chipset_reordering=False,
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host_debug=False):
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self.debug = host_debug
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self.chipset_split = chipset_split
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###
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self.submodules.phy = PHY(dw, endpoint_id, bar0_size, phy_debug)
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self.submodules.chipset = Chipset(self.phy, root_id, chipset_debug, chipset_reordering)
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self.chipset.set_host_callback(self.callback)
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self.rd32_queue = []
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def malloc(self, base, length):
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self.base = base
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self.buffer = [0]*(length//4)
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def write_mem(self, adr, data):
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if self.debug:
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print_host("Writing {} bytes at 0x{:08x}".format(len(data)*4, adr))
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current_adr = (adr-self.base)//4
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for i in range(len(data)):
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self.buffer[current_adr+i] = data[i]
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def read_mem(self, adr, length=1):
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if self.debug:
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print_host("Reading {} bytes at 0x{:08x}".format(length, adr))
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current_adr = (adr-self.base)//4
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data = []
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for i in range(length//4):
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data.append(self.buffer[current_adr+i])
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return data
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def callback(self, msg):
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if isinstance(msg, WR32):
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address = msg.address*4
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self.write_mem(address, msg.data)
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elif isinstance(msg, RD32):
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self.rd32_queue.append(msg)
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def gen_simulation(self, selfp):
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while True:
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if len(self.rd32_queue):
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msg = self.rd32_queue.pop(0)
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address = msg.address*4
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length = msg.length*4
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data = self.read_mem(address, length)
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self.chipset.cmp(msg.requester_id, data, byte_count=length, tag=msg.tag, with_split=self.chipset_split)
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else:
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yield
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