41 lines
1.3 KiB
Python
41 lines
1.3 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.sim.generic import run_simulation
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from misoclib.com.litepcie.core import Endpoint
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from misoclib.com.litepcie.frontend.bridge.wishbone import WishboneBridge
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from misoclib.com.litepcie.test.common import *
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from misoclib.com.litepcie.test.model.host import *
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root_id = 0x100
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endpoint_id = 0x400
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class TB(Module):
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def __init__(self):
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self.submodules.host = Host(64, root_id, endpoint_id,
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phy_debug=False,
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chipset_debug=False,
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host_debug=False)
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self.submodules.endpoint = Endpoint(self.host.phy)
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self.submodules.wishbone_bridge = WishboneBridge(self.endpoint, lambda a: 1)
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self.submodules.sram = wishbone.SRAM(1024, bus=self.wishbone_bridge.wishbone)
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def gen_simulation(self, selfp):
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wr_datas = [seed_to_data(i, True) for i in range(64)]
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for i in range(64):
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yield from self.host.chipset.wr32(i, [wr_datas[i]])
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rd_datas = []
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for i in range(64):
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yield from self.host.chipset.rd32(i)
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rd_datas.append(self.host.chipset.rd32_data[0])
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s, l, e = check(wr_datas, rd_datas)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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