litex/misoclib/mem
2015-08-22 11:47:26 +02:00
..
flash spiflash: fix miso bitbang with large DQ 2015-05-06 00:05:25 +08:00
litesata litecores: add -Ob option to make.py (allow to build with yosys for example) 2015-08-19 01:17:37 +02:00
sdram sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that) 2015-08-22 11:47:26 +02:00
__init__.py