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litex
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176b9240a9
litex
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misoclib
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mem
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sdram
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Sebastien Bourdeauducq
382ed013af
minor cleanups
2015-04-02 14:40:29 +08:00
..
core
minor cleanups
2015-04-02 14:40:29 +08:00
frontend
phy
sdram/phy/simphy: OK with DDR3
2015-03-28 01:59:55 +01:00
test
__init__.py
sdram: remove nbits from modules and databits from GeomSettings
2015-03-26 23:27:37 +01:00
module.py
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
2015-03-28 16:35:15 +01:00