Franck Jullien 179a8018b3 efinix: RGMII phy should be operational (no tested) ... PLL infrastructure should be complete now. We can also use DDIO input and outputs. However, there is problem (bug) during P&R: ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is an output pad but sub-block 1 is not an output pad location. Inderface Designer validation doesn't report any problem. I have a test project with the same configuration (I compared the reports for blocks configuration) and it works.		2021-09-23 17:21:17 +02:00
..
build	efinix: RGMII phy should be operational (no tested)	2021-09-23 17:21:17 +02:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	Add an hacked no we memory for Efinix	2021-09-22 09:47:51 +02:00
soc	efinix: RGMII phy should be operational (no tested)	2021-09-23 17:21:17 +02:00
tools	tools/litex_sim: Fix mem_map.	2021-09-13 11:33:16 +02:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00