Florent Kermarrec 17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)		2016-04-01 00:09:17 +02:00
..
cores	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
integration	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
interconnect	soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores	2016-03-31 00:02:22 +02:00
software	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
tools	soc/tools/litex_term: continue cleanup	2016-02-19 17:44:25 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00