Florent Kermarrec 1d4f44e7db soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores		2016-03-31 00:02:22 +02:00
..
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
csr.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
csr_bus.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
csr_eventmanager.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
dfi.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
dma_lasmi.py	soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)	2016-03-16 20:13:47 +01:00
lasmi_bus.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
stream.py	soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)	2016-03-16 20:13:47 +01:00
stream_packet.py	soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)	2016-03-16 20:13:47 +01:00
stream_sim.py	soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores	2016-03-31 00:02:22 +02:00
wishbone.py	some cleanup	2015-12-27 13:09:58 +01:00
wishbone2csr.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
wishbone2lasmi.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
wishbonebridge.py	soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)	2016-03-16 20:13:47 +01:00