Sebastien Bourdeauducq 1861ae9d01 fhdl/specials: MemoryPort.clock should always be a ClockSignal		2015-09-19 23:21:24 +08:00
..
build	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
fhdl	fhdl/specials: MemoryPort.clock should always be a ClockSignal	2015-09-19 23:21:24 +08:00
genlib	genlib/fifo: add missing import	2015-09-19 23:20:19 +08:00
test	test/fifo: convert to new API	2015-09-19 23:20:30 +08:00
util	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
__init__.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
sim.py	sim: support arrays, and cat+slice in assignment target	2015-09-19 14:56:26 +08:00