litex/misoclib/com/liteeth/phy
2015-03-12 16:57:38 +01:00
..
__init__.py uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty). 2015-03-12 16:57:38 +01:00
gmii.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
loopback.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
mii.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
sim.py liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit 2015-03-09 17:21:29 +01:00