litex/litex/soc/cores
2015-11-16 17:07:22 +01:00
..
cpu for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
flash for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
sdram for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
spi for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
uart soc/cores/uart remove software (will be re-written and will move to soc/tools) 2015-11-16 17:07:22 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
gpio.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
identifier.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
timer.py for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00